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author | Tim Ansell <me@mith.ro> | 2018-10-03 16:38:32 -0700 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-10-08 11:38:10 -0700 |
commit | cd261795ba6942c4d249925fe008db34a8dd46cf (patch) | |
tree | c2b6a4caf14948c8a45d1bf5117e7c4a8c84ec00 | |
parent | b8950bd603aec17c1a0355f1e8d03c0ddecfbe80 (diff) | |
download | yosys-cd261795ba6942c4d249925fe008db34a8dd46cf.tar.gz yosys-cd261795ba6942c4d249925fe008db34a8dd46cf.tar.bz2 yosys-cd261795ba6942c4d249925fe008db34a8dd46cf.zip |
xilinx: Adding missing inout IO port to IOBUF
-rw-r--r-- | techlibs/xilinx/cells_xtra.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index a2dd01ad5..f5abf3ae0 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -2225,6 +2225,7 @@ module IOBUF (...); parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; + inout IO; input I, T; endmodule |