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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 08:19:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 08:19:13 -0800 |
| commit | cd2af66099ed3d4ecc06069b395a577e03113389 (patch) | |
| tree | 55d1b6c58088bf4d8aafdaacc3fce86b60b964c1 | |
| parent | f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26 (diff) | |
| parent | 1c0ee4f786a77d8557c9dd462abc54982b7b639d (diff) | |
| download | yosys-cd2af66099ed3d4ecc06069b395a577e03113389.tar.gz yosys-cd2af66099ed3d4ecc06069b395a577e03113389.tar.bz2 yosys-cd2af66099ed3d4ecc06069b395a577e03113389.zip | |
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
| -rw-r--r-- | passes/hierarchy/submod.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index cf27d2358..b21b0de01 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -34,7 +34,6 @@ struct SubmodWorker RTLIL::Design *design; RTLIL::Module *module; SigMap sigmap; - std::map<RTLIL::SigBit, RTLIL::SigBit> replace_const; bool copy_mode; bool hidden_mode; @@ -231,7 +230,9 @@ struct SubmodWorker if (new_wire->port_id > 0) { // Prevents "ERROR: Mismatch in directionality ..." when flattening if (new_wire->port_output) - old_sig.replace(replace_const); + for (auto &b : old_sig) + if (!b.wire) + b = module->addWire(NEW_ID); new_cell->setPort(new_wire->name, old_sig); } } @@ -265,11 +266,6 @@ struct SubmodWorker if (wire->port_output) sigmap.add(wire); } - auto wire = module->addWire(NEW_ID); - replace_const.emplace(State::S0, wire); - replace_const.emplace(State::S1, wire); - replace_const.emplace(State::Sx, wire); - replace_const.emplace(State::Sz, wire); if (opt_name.empty()) { |