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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:44:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:44:57 -0700 |
| commit | cd5d6940e1c108b26ef4990accfb49fe7d8534c4 (patch) | |
| tree | d5e09f4cf9a7c11baf970b42818b652e5e405a58 | |
| parent | bf046ba09c9f694517a73af28133917e76d4924a (diff) | |
| download | yosys-cd5d6940e1c108b26ef4990accfb49fe7d8534c4.tar.gz yosys-cd5d6940e1c108b26ef4990accfb49fe7d8534c4.tar.bz2 yosys-cd5d6940e1c108b26ef4990accfb49fe7d8534c4.zip | |
Add SB_CARRY to ice40_opt test
| -rw-r--r-- | tests/ice40/ice40_opt.ys | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys index 18e0d2b8a..b17c69c91 100644 --- a/tests/ice40/ice40_opt.ys +++ b/tests/ice40/ice40_opt.ys @@ -1,5 +1,5 @@ read_verilog -icells -formal <<EOT -module top(input CI, I0, output CO, O); +module top(input CI, I0, output [1:0] CO, output O); wire A = 1'b0, B = 1'b0; \$__ICE40_CARRY_WRAPPER #( // A[0]: 1010 1010 1010 1010 @@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O); // A[2]: 1111 0000 1111 0000 // A[3]: 1111 1111 0000 0000 .LUT(~16'b 0110_1001_1001_0110) - ) fadd ( + ) u0 ( .A(A), .B(B), .CI(CI), .I0(I0), .I3(CI), - .CO(CO), + .CO(CO[0]), .O(O) ); + SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1])); endmodule EOT equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt design -load postopt +select -assert-count 1 t:* select -assert-count 1 t:$lut |