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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 12:12:37 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-24 01:07:34 +0100 |
| commit | cde73428b046a1a87339f8a069f59ce732794617 (patch) | |
| tree | 4826a56f9f5a09278678569aa36e735853befef7 | |
| parent | f4f471f34218fb003edf3551406bfd298408094d (diff) | |
| download | yosys-cde73428b046a1a87339f8a069f59ce732794617.tar.gz yosys-cde73428b046a1a87339f8a069f59ce732794617.tar.bz2 yosys-cde73428b046a1a87339f8a069f59ce732794617.zip | |
Fix syntax error in adff2dff.v
Fixes #2600.
| -rw-r--r-- | techlibs/common/adff2dff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v index eca0110eb..2e4357b64 100644 --- a/techlibs/common/adff2dff.v +++ b/techlibs/common/adff2dff.v @@ -11,7 +11,7 @@ module adff2dff (CLK, ARST, D, Q); (* force_downto *) output reg [WIDTH-1:0] Q; (* force_downto *) - wire reg [WIDTH-1:0] NEXT_Q; + reg [WIDTH-1:0] NEXT_Q; wire [1023:0] _TECHMAP_DO_ = "proc;;"; |