diff options
| author | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-20 17:57:26 -0700 |
|---|---|---|
| committer | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-20 17:57:26 -0700 |
| commit | ce069830c5f53643ea9e5bd26c20d13034a164d1 (patch) | |
| tree | dc80fee79be842cf89f5193cad028bc28f48a8e1 | |
| parent | 0ad4321781a53210c42e3450b23f289bc0a35c99 (diff) | |
| download | yosys-ce069830c5f53643ea9e5bd26c20d13034a164d1.tar.gz yosys-ce069830c5f53643ea9e5bd26c20d13034a164d1.tar.bz2 yosys-ce069830c5f53643ea9e5bd26c20d13034a164d1.zip | |
fixing code style
| -rw-r--r-- | passes/equiv/equiv_make.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 8489abe7c..b4905f7c3 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -298,7 +298,7 @@ struct EquivMakeWorker SigSpec new_sig = rd_signal_map(old_sig); if(old_sig != new_sig) { - for(auto & old_bit : old_sig.bits()) { + for (auto &old_bit : old_sig.bits()) { SigBit new_bit = new_sig.bits()[old_bit.offset]; visited_cells.clear(); |