diff options
| author | Claire Wolf <clifford@clifford.at> | 2020-05-01 14:58:41 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-01 14:58:41 +0200 |
| commit | d047ca8b11384dfe8f5d4b63ae7b3e6dfa2d6558 (patch) | |
| tree | 4b1baef137066e17ce882f537853adc27814252a | |
| parent | bc380b0b56e0fa269a0d5844280cc4419d438d3a (diff) | |
| parent | 9f1fb11b1d4d7326c4ba543778993dd6fb655953 (diff) | |
| download | yosys-d047ca8b11384dfe8f5d4b63ae7b3e6dfa2d6558.tar.gz yosys-d047ca8b11384dfe8f5d4b63ae7b3e6dfa2d6558.tar.bz2 yosys-d047ca8b11384dfe8f5d4b63ae7b3e6dfa2d6558.zip | |
Merge pull request #1981 from YosysHQ/claire/fix1837
Clear current_scope when done with RTLIL generation
| -rw-r--r-- | frontends/ast/ast.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 733556621..6a9af3f57 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -946,6 +946,7 @@ RTLIL::Const AstNode::realAsConst(int width) // create a new AstModule from an AST_MODULE AST node static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false) { + log_assert(current_scope.empty()); log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE); if (defer) @@ -1117,6 +1118,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast } ignoreThisSignalsInInitial = RTLIL::SigSpec(); + current_scope.clear(); } else { for (auto &attr : ast->attributes) { @@ -1229,11 +1231,13 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump // process enum/other declarations (*it)->simplify(true, false, false, 1, -1, false, false); design->verilog_packages.push_back((*it)->clone()); + current_scope.clear(); } else { // must be global definition (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations design->verilog_globals.push_back((*it)->clone()); + current_scope.clear(); } } } |