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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 18:10:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 18:10:46 -0700 |
| commit | d06d4f35c376672ad1042b46bb29d7bd2bfa5243 (patch) | |
| tree | b291f3dcc8faf3766f532d5425be08c555fca2da | |
| parent | d7f0700bae9785a55353ca76fe9f354ee4ffe03e (diff) | |
| parent | 7b35d5759289f7a3139c6eaa525ef737b8d5d82b (diff) | |
| download | yosys-d06d4f35c376672ad1042b46bb29d7bd2bfa5243.tar.gz yosys-d06d4f35c376672ad1042b46bb29d7bd2bfa5243.tar.bz2 yosys-d06d4f35c376672ad1042b46bb29d7bd2bfa5243.zip | |
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index ee319b6e6..1a4318460 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1036,7 +1036,7 @@ struct TechmapPass : public Pass { simplemap_get_mappers(worker.simplemap_mappers); std::vector<std::string> map_files; - std::string verilog_frontend = "verilog -nooverwrite"; + std::string verilog_frontend = "verilog -nooverwrite -noblackbox"; int max_iter = -1; size_t argidx; |