diff options
author | David Shah <dave@ds0.me> | 2018-10-18 19:40:02 +0100 |
---|---|---|
committer | David Shah <dave@ds0.me> | 2018-10-19 15:16:40 +0100 |
commit | d29b517fef05973dda3c556a95fbfb478d6e7e50 (patch) | |
tree | d8bb66247d227233d235e3fccba0cb6648264600 | |
parent | 677b8ed3ca70dad1dec288c274e64ebb0ef4011b (diff) | |
download | yosys-d29b517fef05973dda3c556a95fbfb478d6e7e50.tar.gz yosys-d29b517fef05973dda3c556a95fbfb478d6e7e50.tar.bz2 yosys-d29b517fef05973dda3c556a95fbfb478d6e7e50.zip |
ecp5: Sim model fixes
Signed-off-by: David Shah <dave@ds0.me>
-rw-r--r-- | techlibs/ecp5/cells_sim.v | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index e43632c64..6e4b0a5ac 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -265,16 +265,18 @@ module TRELLIS_IO( output O ); parameter DIR = "INPUT"; + reg T_pd; + always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T; generate if (DIR == "INPUT") begin assign B = 1'bz; assign O = B; end else if (DIR == "OUTPUT") begin - assign B = T ? 1'bz : I; + assign B = T_pd ? 1'bz : I; assign O = 1'bx; - end else if (DIR == "INOUT") begin - assign B = T ? 1'bz : I; + end else if (DIR == "BIDIR") begin + assign B = T_pd ? 1'bz : I; assign O = B; end else begin ERROR_UNKNOWN_IO_MODE error(); |