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| author | Claire Xen <claire@symbioticeda.com> | 2020-12-27 16:33:58 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-27 16:33:58 +0100 |
| commit | d30063ea652eba11a0319a1e29e16ac72f814224 (patch) | |
| tree | fb9225125004f77ce5876cbcd3142bb663981b0b | |
| parent | af457ce8d05bb57a48831c3c252c708625ae0ffd (diff) | |
| parent | cb2283389df6fbd2f6aa8393e8d1960123ec72f4 (diff) | |
| download | yosys-d30063ea652eba11a0319a1e29e16ac72f814224.tar.gz yosys-d30063ea652eba11a0319a1e29e16ac72f814224.tar.bz2 yosys-d30063ea652eba11a0319a1e29e16ac72f814224.zip | |
Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast
CODEOWNERS: add @zachjs as Verilog/AST frontend owner
| -rw-r--r-- | CODEOWNERS | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/CODEOWNERS b/CODEOWNERS index 350a62120..0419e6e44 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -25,6 +25,9 @@ passes/opt/opt_lut.cc @whitequark # These still override previous lines, so be careful not to # accidentally disable any of the above rules. +frontends/verilog/ @zachjs +frontends/ast/ @zachjs + techlibs/intel_alm/ @ZirconiumX # pyosys |