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| author | Clifford Wolf <clifford@clifford.at> | 2016-09-14 20:46:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-09-14 20:46:54 +0200 |
| commit | d8ad889594cb5746d3d0b1f7590eeaf63d13c64a (patch) | |
| tree | 9b5539766fef0279db128e12e54d7849abbb714f | |
| parent | d39db41df87113792c383fc2f127a3d42ae6dd0e (diff) | |
| download | yosys-d8ad889594cb5746d3d0b1f7590eeaf63d13c64a.tar.gz yosys-d8ad889594cb5746d3d0b1f7590eeaf63d13c64a.tar.bz2 yosys-d8ad889594cb5746d3d0b1f7590eeaf63d13c64a.zip | |
Bugfix in techmap parameter handling
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1ab6df1dc..b2cc492b2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -639,7 +639,7 @@ struct TechmapWorker if (techmap_cache.count(key) > 0) { tpl = techmap_cache[key]; } else { - if (cell->parameters.size() != 0) { + if (parameters.size() != 0) { derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end())); tpl = map->module(derived_name); log_continue = true; |