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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 17:00:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 15:18:40 -0700 |
| commit | d963e8c2c6207ad98d48dc528922ad58c030173f (patch) | |
| tree | aaf922b06b5d57e2f1ca59dde5cc71b076a9a48f | |
| parent | a274b7cc86d4f64541d3d2903b4eeed4616ab1d8 (diff) | |
| download | yosys-d963e8c2c6207ad98d48dc528922ad58c030173f.tar.gz yosys-d963e8c2c6207ad98d48dc528922ad58c030173f.tar.bz2 yosys-d963e8c2c6207ad98d48dc528922ad58c030173f.zip | |
Fix typo
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 17be28f78..ded1cd60e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const { std::vector<RTLIL::Cell*> result; - result.reserve(wires_.size()); + result.reserve(cells_.size()); for (auto &it : cells_) if (design->selected(this, it.second)) result.push_back(it.second); |