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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-24 15:25:08 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-24 15:25:08 +0100 |
| commit | d9bc024d29dd780e34eb6c9c3e84feab763eeb10 (patch) | |
| tree | 5089202d198ffb0402219e697f820c5d70c1b5ba | |
| parent | e1a80b356e3af1ecd1cdb796ecb0ce2773dbd003 (diff) | |
| download | yosys-d9bc024d29dd780e34eb6c9c3e84feab763eeb10.tar.gz yosys-d9bc024d29dd780e34eb6c9c3e84feab763eeb10.tar.bz2 yosys-d9bc024d29dd780e34eb6c9c3e84feab763eeb10.zip | |
Renamed hansimem.v test case to mem_arst.v
| -rw-r--r-- | tests/simple/mem_arst.v (renamed from tests/simple/hansimem.v) | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/simple/hansimem.v b/tests/simple/mem_arst.v index b02b6c686..4022f57cd 100644 --- a/tests/simple/hansimem.v +++ b/tests/simple/mem_arst.v @@ -21,7 +21,6 @@ module MyMem #( always @(negedge Reset_n_i or posedge Clk_i) begin - //$display("Data1 = %b, Data11 = %b, Data12 = %b, Data2 = %b, Data21 = %b, Data22 = %b",Data1_i,Data11,Data12,Data2_i,Data21,Data22); if (!Reset_n_i) begin Data_o <= 'bx; |