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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 22:47:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 22:47:08 -0700 |
| commit | e0720a8018702a2b4de108363a51c8bffc287b55 (patch) | |
| tree | ef670e3c5a18b673c468c5b6312a71e3d30f2d3d | |
| parent | f9d08a5e5e0ce637b510f6c19a4cd72edf17b3f7 (diff) | |
| download | yosys-e0720a8018702a2b4de108363a51c8bffc287b55.tar.gz yosys-e0720a8018702a2b4de108363a51c8bffc287b55.tar.bz2 yosys-e0720a8018702a2b4de108363a51c8bffc287b55.zip | |
Restore old ffY behaviour
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index fb5fe0951..e4c6238c5 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -3,7 +3,6 @@ pattern ice40_dsp state <SigBit> clock state <bool> clock_pol state <SigSpec> sigA sigB sigY sigS -state <SigSpec> sigYused state <Cell*> addAB muxAB match mul @@ -54,28 +53,18 @@ code sigB clock clock_pol } endcode -// Extract the bits of Y that actually have a consumer -// (as opposed to being a sign extension) -code sigY sigYused - sigY = port(mul, \Y); - int i; - for (i = GetSize(sigY); i > 0; i--) - if (nusers(sigY[i-1]) > 1) - break; - sigYused = sigY.extract(0, i); -endcode - match ffY select ffY->type.in($dff) select nusers(port(ffY, \D)) == 2 - filter param(ffY, \WIDTH).as_int() >= GetSize(sigYused) - filter includes(port(ffY, \D).to_sigbit_set(), sigYused.to_sigbit_set()) + index <SigSpec> port(ffY, \D) === port(mul, \Y) optional endmatch -code clock clock_pol sigY +code sigY clock clock_pol + sigY = port(mul, \Y); + if (ffY) { - sigY.replace(port(ffY, \D), port(ffY, \Q)); + sigY = port(ffY, \Q); SigBit c = port(ffY, \CLK).as_bit(); bool cp = param(ffY, \CLK_POLARITY).as_bool(); |