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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-04 08:01:39 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-04 08:01:39 +0200 |
| commit | e2fb8ebe86f49523168c413c734ce4690d740351 (patch) | |
| tree | 5b6611206bc24d432df8339b22478ef0b847fa36 | |
| parent | 554c58715aa4f8f5ed9fb4293946ac420d3f67a2 (diff) | |
| download | yosys-e2fb8ebe86f49523168c413c734ce4690d740351.tar.gz yosys-e2fb8ebe86f49523168c413c734ce4690d740351.tar.bz2 yosys-e2fb8ebe86f49523168c413c734ce4690d740351.zip | |
Update README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | README.md | 6 |
1 files changed, 1 insertions, 5 deletions
@@ -259,11 +259,7 @@ for them: - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types -- The ``config`` keyword and library map files - -- The ``disable``, ``primitive`` and ``specify`` statements - -- Latched logic (is synthesized as logic with feedback loops) +- The ``config`` and ``disable`` keywords and library map files Verilog Attributes and non-standard features |