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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-13 19:27:49 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-13 19:27:49 +0200 |
| commit | e305d858075902cdfe277f36ce52f8e01de65f7e (patch) | |
| tree | 34c17d1e19e2c4bd9c1f701c76d1bafd16449b79 | |
| parent | 3481f46d1ef66c3dea323bc5a23544f0546dcf44 (diff) | |
| download | yosys-e305d858075902cdfe277f36ce52f8e01de65f7e.tar.gz yosys-e305d858075902cdfe277f36ce52f8e01de65f7e.tar.bz2 yosys-e305d858075902cdfe277f36ce52f8e01de65f7e.zip | |
Added handling of bool-output cells to "wreduce"
| -rw-r--r-- | passes/opt/wreduce.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index fc91f3689..72b4051fa 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -347,6 +347,17 @@ struct WreducePass : public Pass { if (module->has_processes_warn()) continue; + for (auto c : module->selected_cells()) + if (c->type.in({"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", + "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", + "$logic_not", "$logic_and", "$logic_or"}) && GetSize(c->getPort("\\Y")) > 1) { + SigSpec sig = c->getPort("\\Y"); + c->setPort("\\Y", sig[0]); + c->setParam("\\Y_WIDTH", 1); + sig.remove(0); + module->connect(sig, Const(0, GetSize(sig))); + } + WreduceWorker worker(&config, module); worker.run(); } |