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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:17:13 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:17:13 -0700 |
commit | e44042a6410fa32d464ad79013a62ab996242500 (patch) | |
tree | 338962844365a9f15d08ee081f84d88efd3a1834 | |
parent | c5b3830f737310602118851416f9c1931ad91a19 (diff) | |
parent | b5f1bd0df1a467679a93d05604c6cc72696854ba (diff) | |
download | yosys-e44042a6410fa32d464ad79013a62ab996242500.tar.gz yosys-e44042a6410fa32d464ad79013a62ab996242500.tar.bz2 yosys-e44042a6410fa32d464ad79013a62ab996242500.zip |
Merge remote-tracking branch 'origin/master' into xc7mux
-rw-r--r-- | CHANGELOG | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -23,6 +23,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -nopartial" - Added "muxpack" pass - Added "pmux2shiftx -norange" + - Added "synth_xilinx -nocarry" + - Added "synth_xilinx -nowidelut" + - Added "synth_ecp5 -nowidelut" - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) |