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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 11:26:54 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 11:26:54 -0800 |
| commit | e75ca29b19e230bc829a369c7de9cbadb629f5a7 (patch) | |
| tree | 4bdb6776bd77ada7fcefcf9513d82686564dfc3a | |
| parent | 613334d9dcb5c190de8396ff38e2ae73259aa7bf (diff) | |
| download | yosys-e75ca29b19e230bc829a369c7de9cbadb629f5a7.tar.gz yosys-e75ca29b19e230bc829a369c7de9cbadb629f5a7.tar.bz2 yosys-e75ca29b19e230bc829a369c7de9cbadb629f5a7.zip | |
Add test: 'Warning: ignoring initial value on non-register: \o'
| -rw-r--r-- | tests/sat/initval.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..337aa9343 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,3 +2,13 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); +(* init = 1'bx *) +wire p = o; +$_DFF_P_ dff (.C(clk), .D(i), .Q(o)); +endmodule +EOT +sat -seq 1 |