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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-10-10 16:29:27 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-10 16:29:27 +0200 |
| commit | e8ce9442a6a74621e06f30370c75390978c07cc8 (patch) | |
| tree | f1d4417d1c6e82586fccdd7e3abb8c05a9daf686 | |
| parent | d68013811f316f3940110fde8435141279e6db5a (diff) | |
| parent | d29606532a15ae8e0c8d6c3591ccb36652d7339b (diff) | |
| download | yosys-e8ce9442a6a74621e06f30370c75390978c07cc8.tar.gz yosys-e8ce9442a6a74621e06f30370c75390978c07cc8.tar.bz2 yosys-e8ce9442a6a74621e06f30370c75390978c07cc8.zip | |
Merge pull request #3452 from ALGCDG/master
Add BLIF names command input plane size check
| -rw-r--r-- | frontends/blif/blifparse.cc | 9 | ||||
| -rw-r--r-- | tests/blif/bug3385.ys | 9 |
2 files changed, 17 insertions, 1 deletions
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 73d1f0ea7..fe4c9078a 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -21,6 +21,8 @@ YOSYS_NAMESPACE_BEGIN +const int lut_input_plane_limit = 12; + static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f) { string strbuf; @@ -513,6 +515,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool sopmode = -1; lastcell = sopcell; } + else if (input_sig.size() > lut_input_plane_limit) + { + err_reason = stringf("names' input plane must have fewer than %d signals.", lut_input_plane_limit + 1); + goto error_with_reason; + } else { RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut)); @@ -576,7 +583,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (lutptr) { - if (input_len > 12) + if (input_len > lut_input_plane_limit) goto error; for (int i = 0; i < (1 << input_len); i++) { diff --git a/tests/blif/bug3385.ys b/tests/blif/bug3385.ys new file mode 100644 index 000000000..e1e45983d --- /dev/null +++ b/tests/blif/bug3385.ys @@ -0,0 +1,9 @@ +logger -expect error "Syntax error in line 4: names' input plane must have fewer than 13 signals." 1 +read_blif <<EOF +.model test +.inputs w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 w21 w22 w23 w24 w25 w26 w27 w28 w29 w30 +.outputs out +.names w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 w21 w22 w23 w24 w25 w26 w27 w28 w29 w30 out +1101010001100110010001100111001 0 +.end +EOF |