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| author | whitequark <whitequark@whitequark.org> | 2020-08-27 16:34:48 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2020-08-27 16:34:48 +0000 |
| commit | eae88df016cc2134ba822e2a85ab92b955349fbe (patch) | |
| tree | 26b305289626e3aac045950f47a819bf93725702 | |
| parent | a0177569ac4adb36798d29ef5e481614731f4ed0 (diff) | |
| download | yosys-eae88df016cc2134ba822e2a85ab92b955349fbe.tar.gz yosys-eae88df016cc2134ba822e2a85ab92b955349fbe.tar.bz2 yosys-eae88df016cc2134ba822e2a85ab92b955349fbe.zip | |
manual: fix typo.
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 61d628a9c..ed8b4cd49 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -92,7 +92,7 @@ in different stages of the synthesis. \section{The RTL Intermediate Language} -All frontends, passes and backends in Yosys operate on a design in RTLIL} representation. +All frontends, passes and backends in Yosys operate on a design in RTLIL representation. The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL data. |