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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-03-01 12:14:27 -0800 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-03-01 12:14:27 -0800 |
| commit | eccaf101d8324f518ed89134b4f21d2bdc636a8d (patch) | |
| tree | 2a86bbc1c196d1e0b2f9c75fcb038dceca6b2215 | |
| parent | 3090951d54859c331d28232481361bb9c26b3d48 (diff) | |
| download | yosys-eccaf101d8324f518ed89134b4f21d2bdc636a8d.tar.gz yosys-eccaf101d8324f518ed89134b4f21d2bdc636a8d.tar.bz2 yosys-eccaf101d8324f518ed89134b4f21d2bdc636a8d.zip | |
Modify arguments to match existing style.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| -rw-r--r-- | manual/command-reference-manual.tex | 10 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 12 |
2 files changed, 11 insertions, 11 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 257bf7986..bb9d7238c 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -4247,10 +4247,10 @@ compatible with 7-Series Xilinx devices. generate an output netlist (and BLIF file) suitable for VPR. (this feature is experimental and incomplete) - -no-brams - disable infering of block rams + -nobrams + disable infering of block rams - -no-drams + -nodrams disable infering of distributed rams -run <from_label>:<to_label> @@ -4280,11 +4280,11 @@ The following commands are executed by this synthesis command: coarse: synth -run coarse - bram: (only executed when '-no-brams' is not given) + bram: (only executed when '-nobrams' is not given) memory_bram -rules +/xilinx/brams.txt techmap -map +/xilinx/brams_map.v - dram: (only executed when '-no-drams' is not given) + dram: (only executed when '-nodrams' is not given) memory_bram -rules +/xilinx/drams.txt techmap -map +/xilinx/drams_map.v diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 60cfde604..12ad9fdaf 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -no-brams\n"); + log(" -nobrams\n"); log(" disable infering of block rams\n"); log("\n"); - log(" -no-drams\n"); + log(" -nodrams\n"); log(" disable infering of distributed rams\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); @@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass log(" coarse:\n"); log(" synth -run coarse\n"); log("\n"); - log(" bram: (only executed when '-no-brams' is not given)\n"); + log(" bram: (only executed when '-nobrams' is not given)\n"); log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" techmap -map +/xilinx/brams_map.v\n"); log("\n"); - log(" dram: (only executed when '-no-drams' is not given)\n"); + log(" dram: (only executed when '-nodrams' is not given)\n"); log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); @@ -182,11 +182,11 @@ struct SynthXilinxPass : public Pass vpr = true; continue; } - if (args[argidx] == "-no-brams") { + if (args[argidx] == "-nobrams") { noBrams = true; continue; } - if (args[argidx] == "-no-drams") { + if (args[argidx] == "-nodrams") { noDrams = true; continue; } |