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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-13 05:47:55 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-13 05:47:55 +0000 |
| commit | f5d7cd60f56e9890b9a3742ee8c0e6237af23545 (patch) | |
| tree | 76dae3a3c2aaa291c65f4c274726df7cfcc0d373 | |
| parent | b70de98bd1a3141ee56ff991c5bfd6e584cb25e3 (diff) | |
| download | yosys-f5d7cd60f56e9890b9a3742ee8c0e6237af23545.tar.gz yosys-f5d7cd60f56e9890b9a3742ee8c0e6237af23545.tar.bz2 yosys-f5d7cd60f56e9890b9a3742ee8c0e6237af23545.zip | |
splitnets: Clean up pseudo-private member usage
| -rw-r--r-- | passes/cmds/splitnets.cc | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 8d5cd2034..303f084d2 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -174,12 +174,12 @@ struct SplitnetsPass : public Pass { std::map<RTLIL::Wire*, std::set<int>> split_wires_at; - for (auto &c : module->cells_) - for (auto &p : c.second->connections()) + for (auto c : module->cells()) + for (auto &p : c->connections()) { - if (!ct.cell_known(c.second->type)) + if (!ct.cell_known(c->type)) continue; - if (!ct.cell_output(c.second->type, p.first)) + if (!ct.cell_output(c->type, p.first)) continue; RTLIL::SigSpec sig = p.second; @@ -206,9 +206,8 @@ struct SplitnetsPass : public Pass { } else { - for (auto &w : module->wires_) { - RTLIL::Wire *wire = w.second; - if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second)) + for (auto wire : module->wires()) { + if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire)) worker.splitmap[wire] = std::vector<RTLIL::SigBit>(); } |