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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-08 11:32:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-08 11:32:36 +0200 |
| commit | f6b7cf23d65c8e86cbfb742f30167dcc89825cbd (patch) | |
| tree | 4066780fb63d22ce4a021072a5098edb6a7918b5 | |
| parent | e420412043228cec6a15b356cc9eea82bbafe9c0 (diff) | |
| parent | 7c623182393aa2e8445336a99f0cfd4bc7c7e88f (diff) | |
| download | yosys-f6b7cf23d65c8e86cbfb742f30167dcc89825cbd.tar.gz yosys-f6b7cf23d65c8e86cbfb742f30167dcc89825cbd.tar.bz2 yosys-f6b7cf23d65c8e86cbfb742f30167dcc89825cbd.zip | |
Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | backends/blif/blif.cc | 21 |
2 files changed, 24 insertions, 3 deletions
@@ -1,5 +1,5 @@ -CONFIG := clang +CONFIG := icc # CONFIG := gcc # CONFIG := gcc-4.8 # CONFIG := emcc @@ -172,6 +172,10 @@ ABCMKARGS += ARCHFLAGS="-DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -DWIN32 ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="$(CXX)" CXX="$(CXX)" EXE = .exe +else ifeq ($(CONFIG),icc) +CXX = icpc +CXXFLAGS += -std=gnu++0x -Os + else ifneq ($(CONFIG),none) $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, none) endif diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 4484c7584..93953049a 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -93,7 +93,7 @@ struct BlifDumper { std::string str = RTLIL::unescape_id(id); for (size_t i = 0; i < str.size(); i++) - if (str[i] == '#' || str[i] == '=') + if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') str[i] = '?'; cstr_buf.push_back(str); return cstr_buf.back().c_str(); @@ -111,7 +111,7 @@ struct BlifDumper std::string str = RTLIL::unescape_id(sig.wire->name); for (size_t i = 0; i < str.size(); i++) - if (str[i] == '#' || str[i] == '=') + if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') str[i] = '?'; if (sig.wire->width != 1) @@ -207,18 +207,24 @@ struct BlifDumper if (config->false_type != "-") f << stringf(".%s %s %s=$false\n", subckt_or_gate(config->false_type), config->false_type.c_str(), config->false_out.c_str()); + else + f << stringf(".names %s\n", config->false_out.c_str()); } else f << stringf(".names $false\n"); if (!config->true_type.empty()) { if (config->true_type != "-") f << stringf(".%s %s %s=$true\n", subckt_or_gate(config->true_type), config->true_type.c_str(), config->true_out.c_str()); + else + f << stringf(".names %s\n1\n", config->true_out.c_str()); } else f << stringf(".names $true\n1\n"); if (!config->undef_type.empty()) { if (config->undef_type != "-") f << stringf(".%s %s %s=$undef\n", subckt_or_gate(config->undef_type), config->undef_type.c_str(), config->undef_out.c_str()); + else + f << stringf(".names %s\n", config->undef_out.c_str()); } else f << stringf(".names $undef\n"); } @@ -345,13 +351,24 @@ struct BlifDumper f << stringf(" %s", cstr(output)); f << stringf("\n"); RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); + bool one = false; for (int i = 0; i < (1 << width); i++) if (mask[i] == RTLIL::S1) { for (int j = width-1; j >= 0; j--) { f << ((i>>j)&1 ? '1' : '0'); } f << " 1\n"; + one = true; } + /* For some reason, sometimes we get LUTs with + * an all zero mask, which won't give any + * .names entries, so write one entry with + * all don't cares */ + if (!one) { + for (int j = width-1; j >= 0; j--) + f << '-'; + f << " 0\n"; + } continue; } |