Fix comments

8 files changed, 11 insertions, 10 deletions

diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys
index 8eeb221db..4a998d98d 100644
--- a/tests/ice40/add_sub.ys
+++ b/tests/ice40/add_sub.ys
@@ -1,6 +1,6 @@
 read_verilog add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 11 t:SB_LUT4
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index 3c676e590..14b251c5c 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,8 +1,8 @@
 read_verilog adffs.v
 proc
-async2sync
+async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
index b14346f5a..ee7f884b1 100644
--- a/tests/ice40/dffs.ys
+++ b/tests/ice40/dffs.ys
@@ -2,7 +2,7 @@ read_verilog dffs.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 613cad760..96753b4ef 100644
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -1,7 +1,7 @@
 read_verilog div_mod.v
 hierarchy -top top
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 88 t:SB_LUT4
diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys
index 0a8c48dca..fa5d004b0 100644
--- a/tests/ice40/memory.ys
+++ b/tests/ice40/memory.ys
@@ -2,4 +2,5 @@ read_verilog memory.v
 synth_ice40
 cd top
 select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D
 write_verilog memory_synth.v
diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys
index aec7d0b1f..8a0822a84 100644
--- a/tests/ice40/mul.ys
+++ b/tests/ice40/mul.ys
@@ -1,6 +1,6 @@
 read_verilog mul.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys
index 63d22001f..182b49499 100644
--- a/tests/ice40/mux.ys
+++ b/tests/ice40/mux.ys
@@ -1,8 +1,8 @@
 read_verilog mux.v
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
-design -load postopt
-cd top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
 select -assert-count 19 t:SB_LUT4
 select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
index 8049a37ab..ef4266959 100644
--- a/tests/ice40/tribuf.ys
+++ b/tests/ice40/tribuf.ys
@@ -2,7 +2,7 @@ read_verilog tribuf.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_