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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 20:14:24 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 20:14:24 -0800 |
| commit | fad99c2ec7bd4bceaf5a2c1c5e93f83c85b81720 (patch) | |
| tree | deffe7731d8abbd5d20ca511a1ff2e6412cfa612 | |
| parent | b42b64e8ed713b0e9810f18db7cafcf356e2b4f6 (diff) | |
| parent | 0c4be94a02a70de495343258ecda19eb20b3616b (diff) | |
| download | yosys-fad99c2ec7bd4bceaf5a2c1c5e93f83c85b81720.tar.gz yosys-fad99c2ec7bd4bceaf5a2c1c5e93f83c85b81720.tar.bz2 yosys-fad99c2ec7bd4bceaf5a2c1c5e93f83c85b81720.zip | |
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
| -rw-r--r-- | passes/techmap/abc9.cc | 9 | ||||
| -rw-r--r-- | tests/arch/xilinx/abc9_map.ys | 8 |
2 files changed, 4 insertions, 13 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7d922df56..9e1318700 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -124,15 +124,6 @@ struct Abc9Pass : public ScriptPass log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n"); log("if you want to use ABC to convert your design into another format.\n"); log("\n"); - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("Delay targets can also be specified on a per clock basis by attaching a\n"); - log("'(* abc9_period = <int> *)' attribute onto clock wires (specifically, onto wires\n"); - log("that appear inside any special '$abc9_clock' wires inserted by abc9_map.v). This\n"); - log("can be achieved by modifying the source directly, or through a `setattr`\n"); - log("invocation. Since such attributes cannot yet be propagated through a\n"); - log("hierarchical design (whether or not it has been uniquified) it is recommended\n"); - log("that the design be flattened when using this feature.\n"); - log("\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); help_script(); diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys index 6823589f1..4a7b9384a 100644 --- a/tests/arch/xilinx/abc9_map.ys +++ b/tests/arch/xilinx/abc9_map.ys @@ -6,7 +6,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDSE select -assert-count 1 t:FDSE_1 @@ -29,7 +29,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 @@ -52,7 +52,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDCE select -assert-count 1 t:FDCE_1 @@ -76,7 +76,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDPE techmap -autoproc -map +/xilinx/cells_sim.v |