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| author | Oliver Keszöcze <github@keszoecze.de> | 2023-02-17 17:54:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-17 17:54:41 +0100 |
| commit | fc56978703b5e942ba728970e13e065100a34cd7 (patch) | |
| tree | 5f6cca5a223055741e7041baf1181e68ebf4af96 | |
| parent | 1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7 (diff) | |
| download | yosys-fc56978703b5e942ba728970e13e065100a34cd7.tar.gz yosys-fc56978703b5e942ba728970e13e065100a34cd7.tar.bz2 yosys-fc56978703b5e942ba728970e13e065100a34cd7.zip | |
Check DREG attribute
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ee5a89e22..e6e15b16e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -3614,7 +3614,7 @@ module DSP48E1 ( if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end else always @* Cr <= C; - if (CREG == 1) initial Dr = 25'b0; + if (DREG == 1) initial Dr = 25'b0; if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end else always @* Dr <= D; |