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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:15:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:15:53 -0700 |
| commit | fc5fda595d2695d1f29f68f0527052e99c301db8 (patch) | |
| tree | 567476466c7787341cd8655cab6a5031224ed7b3 | |
| parent | fed1f0ba637941cc0c2c4cc75c08ba7e3994c1a0 (diff) | |
| parent | 0c8a839f13bf7bc8368625ab55960dd3f219b0d8 (diff) | |
| download | yosys-fc5fda595d2695d1f29f68f0527052e99c301db8.tar.gz yosys-fc5fda595d2695d1f29f68f0527052e99c301db8.tar.bz2 yosys-fc5fda595d2695d1f29f68f0527052e99c301db8.zip | |
Merge branch 'xaig' into xc7mux
| -rw-r--r-- | passes/techmap/abc9.cc | 3 | ||||
| -rwxr-xr-x | tests/simple_abc9/run-test.sh | 1 |
2 files changed, 1 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f5f7add9a..b14eef485 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -414,8 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); - // Adopt same behaviour as abc - // TODO: How to specify don't-care to abc9? + // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero Pass::call(design, "setundef -zero"); Pass::call(design, "aigmap"); diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index bf48d007d..af003d52e 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then fi cp ../simple/*.v . -rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails DOLLAR='?' exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'" |