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| author | Jannis Harder <me@jix.one> | 2022-11-02 17:58:49 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-29 19:06:45 +0100 |
| commit | fd56d1f79e8bd539cb63a03cb20210fc29fd2c19 (patch) | |
| tree | 40e937dd8ca9eaa951771a89aec582695aba13c2 | |
| parent | c08242ba413302d76cc4986ad972c29a510d6990 (diff) | |
| download | yosys-fd56d1f79e8bd539cb63a03cb20210fc29fd2c19.tar.gz yosys-fd56d1f79e8bd539cb63a03cb20210fc29fd2c19.tar.bz2 yosys-fd56d1f79e8bd539cb63a03cb20210fc29fd2c19.zip | |
opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells
| -rw-r--r-- | passes/opt/opt_expr.cc | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 38b0d221b..f05d53271 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1527,6 +1527,31 @@ skip_identity: goto next_cell; \ } \ } +#define FOLD_2ARG_SIMPLE_CELL(_t, B_ID) \ + if (cell->type == ID($##_t)) { \ + RTLIL::SigSpec a = cell->getPort(ID::A); \ + RTLIL::SigSpec b = cell->getPort(B_ID); \ + assign_map.apply(a), assign_map.apply(b); \ + if (a.is_fully_const() && b.is_fully_const()) { \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const())); \ + cover("opt.opt_expr.const.$" #_t); \ + replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \ + goto next_cell; \ + } \ + } +#define FOLD_MUX_CELL(_t) \ + if (cell->type == ID($##_t)) { \ + RTLIL::SigSpec a = cell->getPort(ID::A); \ + RTLIL::SigSpec b = cell->getPort(ID::B); \ + RTLIL::SigSpec s = cell->getPort(ID::S); \ + assign_map.apply(a), assign_map.apply(b), assign_map.apply(s); \ + if (a.is_fully_const() && b.is_fully_const() && s.is_fully_const()) { \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), s.as_const())); \ + cover("opt.opt_expr.const.$" #_t); \ + replace_cell(assign_map, module, cell, stringf("%s, %s, %s", log_signal(a), log_signal(b), log_signal(s)), ID::Y, y); \ + goto next_cell; \ + } \ + } FOLD_1ARG_CELL(not) FOLD_2ARG_CELL(and) @@ -1558,6 +1583,9 @@ skip_identity: FOLD_2ARG_CELL(gt) FOLD_2ARG_CELL(ge) + FOLD_2ARG_CELL(eqx) + FOLD_2ARG_CELL(nex) + FOLD_2ARG_CELL(add) FOLD_2ARG_CELL(sub) FOLD_2ARG_CELL(mul) @@ -1570,6 +1598,11 @@ skip_identity: FOLD_1ARG_CELL(pos) FOLD_1ARG_CELL(neg) + FOLD_MUX_CELL(mux); + FOLD_MUX_CELL(pmux); + FOLD_2ARG_SIMPLE_CELL(bmux, ID::S); + FOLD_2ARG_SIMPLE_CELL(demux, ID::S); + // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == ID($mux)) { RTLIL::SigSpec input = assign_map(cell->getPort(ID::S)); |