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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 13:38:32 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 13:38:32 -0800 |
| commit | ff2645ce0b8d0e639b0e83db35476036dde34f0d (patch) | |
| tree | 38f12f51a8490d80fe907193a50db40082c491d6 | |
| parent | 1482f32d53da84ddfb034cff88174af5e5c41761 (diff) | |
| download | yosys-ff2645ce0b8d0e639b0e83db35476036dde34f0d.tar.gz yosys-ff2645ce0b8d0e639b0e83db35476036dde34f0d.tar.bz2 yosys-ff2645ce0b8d0e639b0e83db35476036dde34f0d.zip | |
Put specify/endspecify inside ``
| -rw-r--r-- | README.md | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -454,10 +454,10 @@ Verilog Attributes and non-standard features expressions over parameters and constant values are allowed). The intended use for this is synthesis-time DRC. -- There is limited support for converting specify .. endspecify statements to - special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in - blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this - functionality. (By default specify .. endspecify blocks are ignored.) +- There is limited support for converting ``specify`` .. ``endspecify`` + statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, + for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to + enable this functionality. (By default these blocks are ignored.) Non-standard or SystemVerilog features for formal verification |