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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:31:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:31:48 -0700 |
| commit | 1b08f861b6f95dba561ec48f71d3ab5bc18f64f2 (patch) | |
| tree | b08eebb56cfa49743504bfcb97d3778dedc13d9d /CHANGELOG | |
| parent | 8d820a9884c0a58ee7817a2052d8b915578a7ba7 (diff) | |
| parent | 52c4655de32c027e0542834d030ac951be10c8eb (diff) | |
| download | yosys-1b08f861b6f95dba561ec48f71d3ab5bc18f64f2.tar.gz yosys-1b08f861b6f95dba561ec48f71d3ab5bc18f64f2.tar.bz2 yosys-1b08f861b6f95dba561ec48f71d3ab5bc18f64f2.zip | |
Merge branch 'eddie/xilinx_srl' into xaig_arrival
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -36,6 +36,8 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping - Removed "ice40_unlut" - Improvements in pmgen: slices, choices, define, generate + - Added "xilinx_srl" for Xilinx shift register extraction + - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") Yosys 0.8 .. Yosys 0.9 ---------------------- |