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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:54:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:54:34 -0700 |
| commit | 440f173aef421f30c6ce63822532dbb8a1b231af (patch) | |
| tree | ec14c261f6efb62e6c9c8f0460c2c6f32d874419 /CHANGELOG | |
| parent | 83f143015bc21423877d5074f11ce156073dfdf1 (diff) | |
| parent | eab8384ec7108db62573567f9fbceca62adfdbe5 (diff) | |
| download | yosys-440f173aef421f30c6ce63822532dbb8a1b231af.tar.gz yosys-440f173aef421f30c6ce63822532dbb8a1b231af.tar.bz2 yosys-440f173aef421f30c6ce63822532dbb8a1b231af.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -dmux=<cost>" - Added "muxcover -nopartial" - Added "muxpack" pass + - Added "pmux2shiftx -norange" - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) @@ -51,7 +52,7 @@ Yosys 0.7 .. Yosys 0.8 - Added Verilog $rtoi and $itor support - Added "check -initdrv" - Added "read_blif -wideports" - - Added support for systemVerilog "++" and "--" operators + - Added support for SystemVerilog "++" and "--" operators - Added support for SystemVerilog unique, unique0, and priority case - Added "write_edif" options for edif "flavors" - Added support for resetall compiler directive |