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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
| commit | 6f36ec8ecf147f8d669f35dd616714af971db6f4 (patch) | |
| tree | 04dc0222fd51dd70edef52b733cecd2a9179c093 /CHANGELOG | |
| parent | d2fed0a7f1bb72ee285657b974f4996c77641a23 (diff) | |
| parent | ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 (diff) | |
| download | yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.gz yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.bz2 yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -21,6 +21,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -mux{4,8,16}=<cost>" - Added "muxcover -dmux=<cost>" - Added "muxcover -nopartial" + - Added "muxpack" pass - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) |