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| author | Jannis Harder <me@jix.one> | 2022-05-24 14:32:14 +0200 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-05-24 23:03:31 -0400 |
| commit | cffec1f95f0ac4bad1deb24bf7f921bd93145a16 (patch) | |
| tree | c66eeb0e812b0519e8f72791c70e2b6dc44d7df3 /CHANGELOG | |
| parent | c525b5f91925bd51194ead99a4ecace313f9945c (diff) | |
| download | yosys-cffec1f95f0ac4bad1deb24bf7f921bd93145a16.tar.gz yosys-cffec1f95f0ac4bad1deb24bf7f921bd93145a16.tar.bz2 yosys-cffec1f95f0ac4bad1deb24bf7f921bd93145a16.zip | |
verilog: fix signedness when removing unreachable cases
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -5,6 +5,11 @@ List of major changes and improvements between releases Yosys 0.17 .. Yosys 0.17-dev -------------------------- + * Verilog + - Fixed an issue where simplifying case statements by removing unreachable + cases could result in the wrong signedness being used for comparison with + the remaining cases + Yosys 0.16 .. Yosys 0.17 -------------------------- * New commands and options |