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authorArchie <ac11018@ic.ac.uk>2022-08-21 17:18:20 -0500
committerArchie <ac11018@ic.ac.uk>2022-08-21 17:18:20 -0500
commitdb73f3c26b2768f93c7573b7c7d74b1cc7a0756d (patch)
tree81696fd98770e519aea96fe3a6e40bcc3b3a4360 /CHANGELOG
parente7e8e3b0f65ea1ebfcf04bffd0d9ba90f8e0d7fe (diff)
parent029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff)
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Merge branch 'master' of https://github.com/ALGCDG/yosys
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List of major changes and improvements between releases
=======================================================
-Yosys 0.18 .. Yosys 0.18-dev
+Yosys 0.20 .. Yosys 0.20-dev
--------------------------
+ * New commands and options
+ - Added "formalff" pass - transforms FFs for formal verification
+ - Added option "-formal" to "memory_map" pass
+ - Added option "-witness" to "rename" - give public names to all signals
+ present in yosys witness traces
+ - Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
+ simulation output for a flattened design
+
+ * Formal Verification
+ - Added $anyinit cell to directly represent FFs with an unconstrained
+ initialization value. These can be generated by the new formalff pass.
+ - New JSON based yosys witness format for formal verification traces.
+ - yosys-smtbmc: Reading and writing of yosys witness traces.
+ - write_smt2: Emit inline metadata to support yosys witness trace.
+ - yosys-witness is a new tool to inspect and convert yosys witness traces.
+ - write_aiger: Option to write a map file for yosys witness trace
+ conversion.
+ - yosys-witness: Conversion from and to AIGER witness traces.
+
+Yosys 0.19 .. Yosys 0.20
+--------------------------
+ * New commands and options
+ - Added option "-wb" to "read_liberty" pass
+
+ * Various
+ - Added support for $modfloor operator to cxxrtl backend
+ - Support build on OpenBSD
+ - Fixed smt2 backend use of $shift/$shiftx with negative shift amounts,
+ which affects bit/part-select assignments with a dynamic index. Shift
+ operators were not affected.
+
+ * Verific support
+ - Proper import of port ranges into Yosys, may result in reversed
+ bit-order of top-level ports for some synthesis flows.
+
+Yosys 0.18 .. Yosys 0.19
+--------------------------
+ * New commands and options
+ - Added option "-rom-only" to "memory_libmap" pass
+ - Added option "-smtcheck" to "hierarchy" pass
+ - Added option "-keepdc" to "memory_libmap" pass
+ - Added option "-suffix" to "rename" pass
+ - Added "gatemate_foldinv" pass
+
+ * Formal Verification
+ - Added support for $pos cell in btor backend
+ - Added the "smtlib2_module" and "smtlib2_comb_expr" attributes
+
+ * GateMate support
+ - Added LUT tree mapping
+
+ * Verific support
+ - Added option "-pp" to "verific -import"
Yosys 0.17 .. Yosys 0.18
--------------------------