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| author | Clifford Wolf <clifford@clifford.at> | 2018-03-08 13:26:33 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-08 13:26:33 +0100 |
| commit | a15208f3012a20ad493850a7072fa501b917a67f (patch) | |
| tree | 08c98c3fd7d10133de63893d1f8322637fb2d65c /Makefile | |
| parent | 8b604004dae31f7f3120685dd05d16a4bace904a (diff) | |
| download | yosys-a15208f3012a20ad493850a7072fa501b917a67f.tar.gz yosys-a15208f3012a20ad493850a7072fa501b917a67f.tar.bz2 yosys-a15208f3012a20ad493850a7072fa501b917a67f.zip | |
Use Verific hier_tree component for elaboration
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -279,7 +279,7 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib_eval -VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf +VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz endif |