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| author | Claire Wolf <clifford@clifford.at> | 2020-05-07 18:11:48 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-07 18:11:48 +0200 |
| commit | 06104249406972de01d0360df63a32cafcdf2ec5 (patch) | |
| tree | 22b352c1ebf2289e7cc61561d233501762742580 /README.md | |
| parent | 3a985d82851e498ba768d46403c41c05e5897eb4 (diff) | |
| parent | 885deb4e88e847e1314b8a67087f72c3809a6995 (diff) | |
| download | yosys-06104249406972de01d0360df63a32cafcdf2ec5.tar.gz yosys-06104249406972de01d0360df63a32cafcdf2ec5.tar.bz2 yosys-06104249406972de01d0360df63a32cafcdf2ec5.zip | |
Merge pull request #2005 from YosysHQ/claire/fix1990
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -281,6 +281,9 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by Yosys to synthesize Verilog functions and access arrays. +- The ``nowrshmsk`` attribute on a register prohibits the generation of + shift-and-mask type circuits for writing to bit slices of that register. + - The ``onehot`` attribute on wires mark them as one-hot state register. This is used for example for memory port sharing and set by the fsm_map pass. |