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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 07:57:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 07:57:17 -0700 |
| commit | 0642baabbceaf4e34ae03c47136ed987b976cdbb (patch) | |
| tree | c1fc9032ecd71c13b9ec5ab3fcb844dd0ceb1313 /README.md | |
| parent | 9a6da9a79a22e984ee3eec02caa230b66f10e11a (diff) | |
| parent | ea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 (diff) | |
| download | yosys-0642baabbceaf4e34ae03c47136ed987b976cdbb.tar.gz yosys-0642baabbceaf4e34ae03c47136ed987b976cdbb.tar.bz2 yosys-0642baabbceaf4e34ae03c47136ed987b976cdbb.zip | |
Merge branch 'master' into eddie/fix_retime
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -312,10 +312,10 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. -- The ``dynports'' attribute is used by the Verilog front-end to mark modules +- The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- The ``hdlname'' attribute is used by some passes to document the original +- The ``hdlname`` attribute is used by some passes to document the original (HDL) name of a module when renaming a module. - The ``keep`` attribute on cells and wires is used to mark objects that should |