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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 13:56:13 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 13:56:13 -0800 |
| commit | 1ea1e8e54f33e4a048c1343959e20e8f1c8ad73b (patch) | |
| tree | a5ac3ee416f3c74c7e842a88c691a61588c49c01 /README.md | |
| parent | 45f0f1486bbe30cdbf22c94b165879568af1a37a (diff) | |
| parent | 7928eb113c5a310924f4bb8ab26d0dafe902d6ec (diff) | |
| download | yosys-1ea1e8e54f33e4a048c1343959e20e8f1c8ad73b.tar.gz yosys-1ea1e8e54f33e4a048c1343959e20e8f1c8ad73b.tar.bz2 yosys-1ea1e8e54f33e4a048c1343959e20e8f1c8ad73b.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -454,10 +454,10 @@ Verilog Attributes and non-standard features expressions over parameters and constant values are allowed). The intended use for this is synthesis-time DRC. -- There is limited support for converting specify .. endspecify statements to - special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in - blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this - functionality. (By default specify .. endspecify blocks are ignored.) +- There is limited support for converting ``specify`` .. ``endspecify`` + statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, + for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to + enable this functionality. (By default these blocks are ignored.) Non-standard or SystemVerilog features for formal verification |