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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-19 13:53:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-19 13:53:07 +0200 |
| commit | 5a1f1caa44fb3f4427813acab61aaecc06bae7ba (patch) | |
| tree | 3cceea7d49a6ae44e5ab765e0bd11fecfee6b47b /README.md | |
| parent | c330379870a48209534807d1c021ce2a20ccf880 (diff) | |
| parent | fa5fc3f6afd9eb27c1f52244b60cbeb77aa2e26c (diff) | |
| download | yosys-5a1f1caa44fb3f4427813acab61aaecc06bae7ba.tar.gz yosys-5a1f1caa44fb3f4427813acab61aaecc06bae7ba.tar.bz2 yosys-5a1f1caa44fb3f4427813acab61aaecc06bae7ba.zip | |
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Improve handling of initial/default values
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -350,6 +350,10 @@ Verilog Attributes and non-standard features through the synthesis. When entities are combined, a new |-separated string is created that contains all the string from the original entities. +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |