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| author | Claire Wolf <clifford@clifford.at> | 2020-05-01 15:35:33 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-01 15:35:33 +0200 |
| commit | 667f38fe533c9f6676b5944d801a5fb33938ef8b (patch) | |
| tree | 91651b2f39a59eb736bc5eb21393eca7ebd04c92 /README.md | |
| parent | d047ca8b11384dfe8f5d4b63ae7b3e6dfa2d6558 (diff) | |
| parent | 9b26a1fa89e34af8651af381d88088b738c75769 (diff) | |
| download | yosys-667f38fe533c9f6676b5944d801a5fb33938ef8b.tar.gz yosys-667f38fe533c9f6676b5944d801a5fb33938ef8b.tar.bz2 yosys-667f38fe533c9f6676b5944d801a5fb33938ef8b.zip | |
Merge pull request #1997 from whitequark/document-ootb
Explain how to do out-of-tree builds in README
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 9 |
1 files changed, 8 insertions, 1 deletions
@@ -118,6 +118,13 @@ Tests are located in the tests subdirectory and can be executed using the test t $ make test +To use a separate (out-of-tree) build directory, provide a path to the Makefile. + + $ mkdir build; cd build + $ make -f ../Makefile + +Out-of-tree builds require a clean source tree. + Getting Started =============== @@ -388,7 +395,7 @@ Verilog Attributes and non-standard features - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete - connections to matching wires in ``hierarchy``. + connections to matching wires in ``hierarchy``. - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes |