diff options
author | Marcin KoĆcielnicki <koriakin@0x04.net> | 2019-11-24 16:05:45 +0100 |
---|---|---|
committer | Marcin KoĆcielnicki <mwk@0x04.net> | 2019-11-25 20:40:39 +0100 |
commit | 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d (patch) | |
tree | 479662c910620126719f95acbd2ab7893496e1ed /README.md | |
parent | 7562e7304e2592ddd5a914ec723a6563c14141e0 (diff) | |
download | yosys-6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d.tar.gz yosys-6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d.tar.bz2 yosys-6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d.zip |
clkbufmap: Add support for inverters in clock path.
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -343,6 +343,13 @@ Verilog Attributes and non-standard features - The ``clkbuf_sink`` attribute can be set on an input port of a module to request clock buffer insertion by the ``clkbufmap`` pass. +- The ``clkbuf_inv`` attribute can be set on an output port of a module + with the value set to the name of an input port of that module. When + the ``clkbufmap`` would otherwise insert a clock buffer on this output, + it will instead try inserting the clock buffer on the input port (this + is used to implement clock inverter cells that clock buffer insertion + will "see through"). + - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent automatic clock buffer insertion by ``clkbufmap``. This behaviour can be overridden by providing a custom selection to ``clkbufmap``. |