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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 09:59:57 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 09:59:57 -0700 |
| commit | c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537 (patch) | |
| tree | 458a1aa6479b55a1463dd3d372af651c691e4352 /README.md | |
| parent | d81a090d89d87837d3e18f9c724fe5c89ddf1f64 (diff) | |
| download | yosys-c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537.tar.gz yosys-c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537.tar.bz2 yosys-c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537.zip | |
Update doc
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -417,9 +417,10 @@ Verilog Attributes and non-standard features port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths as a combinatorial loop. -- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark - the carry-in and carry-out ports of a box. This information is necessary for - `abc9` to preserve the integrity of carry-chains. +- The port attribute ``abc_carry`` marks the carry-in (if an input port) and + carry-out (if output port) ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. Specifying this attribute + onto a bus port will affect its most significant bit. Non-standard or SystemVerilog features for formal verification |