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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-28 14:58:14 +0000 |
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| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-19 04:02:48 +0200 |
| commit | c9f9518de4af34b2539d230c0894b04d174b755d (patch) | |
| tree | c4c4062344d55f7ef4935ef6f68475b7f233722f /README.md | |
| parent | 70c607d7dde23b709ffd36c47680cddcc4666fcd (diff) | |
| download | yosys-c9f9518de4af34b2539d230c0894b04d174b755d.tar.gz yosys-c9f9518de4af34b2539d230c0894b04d174b755d.tar.bz2 yosys-c9f9518de4af34b2539d230c0894b04d174b755d.zip | |
Added extractinv pass
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -347,6 +347,12 @@ Verilog Attributes and non-standard features automatic clock buffer insertion by ``clkbufmap``. This behaviour can be overridden by providing a custom selection to ``clkbufmap``. +- The ``invertible_pin`` attribute can be set on a port to mark it as + invertible via a cell parameter. The name of the inversion parameter + is specified as the value of this attribute. The value of the inversion + parameter must be of the same width as the port, with 1 indicating + an inverted bit and 0 indicating a non-inverted bit. + - The ``iopad_external_pin`` attribute on a blackbox module's port marks it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. |