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author | whitequark <whitequark@whitequark.org> | 2020-12-11 23:30:32 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-12-11 23:32:06 +0000 |
commit | e4aa8bc96b1650ef17d70a0ba7cd88b21b7e38dc (patch) | |
tree | b209e2e462f3fa72fbd9533c706a4afeed098680 /README.md | |
parent | ec410c9b1934c5c06ad6f71e60f2337fabe5b055 (diff) | |
download | yosys-e4aa8bc96b1650ef17d70a0ba7cd88b21b7e38dc.tar.gz yosys-e4aa8bc96b1650ef17d70a0ba7cd88b21b7e38dc.tar.bz2 yosys-e4aa8bc96b1650ef17d70a0ba7cd88b21b7e38dc.zip |
cxxrtl: don't overwrite buffered inputs.
Before this commit, a cell's input was always assigned like:
p_cell.p_input = (value...);
If `p_input` is buffered (e.g. if the design is built at -O0), this
is not correct. (In practice, this breaks clocking.) Unfortunately,
the incorrect design was compiled without diagnostics because wire<>
was move-assignable and also implicitly constructible from value<>.
After this commit, cell inputs are no longer incorrectly assumed to
always be unbuffered, and wires are not assignable from values.
Diffstat (limited to 'README.md')
0 files changed, 0 insertions, 0 deletions