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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-05 15:52:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-05 15:52:29 +0100 |
| commit | 1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a (patch) | |
| tree | 40df3df37aa20b06ea948a4eb1a5793def05c2cd /README | |
| parent | 27fec4e77c8d116deb90398400f5f2a1eb5cf785 (diff) | |
| download | yosys-1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a.tar.gz yosys-1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a.tar.bz2 yosys-1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a.zip | |
Added support for "keep" attributes on wires
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -254,9 +254,9 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The verilog backend also does not output placeholder modules on default. -- The "keep" attribute on cells is used to mark cells that should never be - removed by the optimizer. This is used for example for cells that have - hidden connections that are not part of the netlist, such as IO pads. +- The "keep" attribute on cells and wires is used to mark objects that should + never be removed by the optimizer. This is used for example for cells that + have hidden connections that are not part of the netlist, such as IO pads. - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes |