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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 15:14:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 15:14:31 -0700 |
| commit | 8f5710c464b2b3b91f0c7f29a9420dcb798be4c5 (patch) | |
| tree | 59bde082cba0f8f76e0e297ed57980592df7e73b /backends/aiger/aiger.cc | |
| parent | f1a206ba03c5b6fba2672754d09cc649a60beeb8 (diff) | |
| parent | fd0e3a2c43d96ba31beede9865d5000230029994 (diff) | |
| download | yosys-8f5710c464b2b3b91f0c7f29a9420dcb798be4c5.tar.gz yosys-8f5710c464b2b3b91f0c7f29a9420dcb798be4c5.tar.bz2 yosys-8f5710c464b2b3b91f0c7f29a9420dcb798be4c5.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'backends/aiger/aiger.cc')
| -rw-r--r-- | backends/aiger/aiger.cc | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 7c851bb91..0798fb35d 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -101,7 +101,7 @@ struct AigerWriter return a; } - AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module) + AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module) { pool<SigBit> undriven_bits; pool<SigBit> unused_bits; @@ -367,6 +367,12 @@ struct AigerWriter aig_latchin.push_back(a); } + if (lmode && aig_l == 0) { + aig_m++, aig_l++; + aig_latchinit.push_back(0); + aig_latchin.push_back(0); + } + if (!initstate_bits.empty() || !init_inputs.empty()) aig_latchin.push_back(1); @@ -704,9 +710,9 @@ struct AigerBackend : public Backend { log(" -vmap <filename>\n"); log(" like -map, but more verbose\n"); log("\n"); - log(" -I, -O, -B\n"); - log(" If the design contains no input/output/assert then create one\n"); - log(" dummy input/output/bad_state pin to make the tools reading the\n"); + log(" -I, -O, -B, -L\n"); + log(" If the design contains no input/output/assert/flip-flop then create one\n"); + log(" dummy input/output/bad_state-pin or latch to make the tools reading the\n"); log(" AIGER file happy.\n"); log("\n"); } @@ -720,6 +726,7 @@ struct AigerBackend : public Backend { bool imode = false; bool omode = false; bool bmode = false; + bool lmode = false; std::string map_filename; log_header(design, "Executing AIGER backend.\n"); @@ -764,6 +771,10 @@ struct AigerBackend : public Backend { bmode = true; continue; } + if (args[argidx] == "-L") { + lmode = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -773,7 +784,7 @@ struct AigerBackend : public Backend { if (top_module == nullptr) log_error("Can't find top module in current design!\n"); - AigerWriter writer(top_module, zinit_mode, imode, omode, bmode); + AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode); writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode); if (!map_filename.empty()) { |