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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 09:51:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 09:51:43 -0700 |
| commit | 36e2eb06bb63714d852b758062471222022930c3 (patch) | |
| tree | 72139916594c7b67d5f7a1a4e7c5ab6b56d6cde4 /backends/aiger | |
| parent | 03705f69f4e7fbd19181297cd4de68472a5f4ba3 (diff) | |
| download | yosys-36e2eb06bb63714d852b758062471222022930c3.tar.gz yosys-36e2eb06bb63714d852b758062471222022930c3.tar.bz2 yosys-36e2eb06bb63714d852b758062471222022930c3.zip | |
Fix more potential for undefined behaviour due to container invalidation
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ae690ec49..d373ca77e 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -436,14 +436,18 @@ struct XAigerWriter new_wire = module->addWire(wire_name, GetSize(wire)); SigBit new_bit(new_wire, bit.offset); module->connect(new_bit, bit); - if (not_map.count(bit)) - not_map[new_bit] = not_map.at(bit); + if (not_map.count(bit)) { + auto a = not_map.at(bit); + not_map[new_bit] = a; + } else if (and_map.count(bit)) { - //and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8 - and_map.insert(std::make_pair(new_bit, and_map.at(bit))); + auto a = and_map.at(bit); + and_map[new_bit] = a; + } + else if (alias_map.count(bit)) { + auto a = alias_map.at(bit); + alias_map[new_bit] = a; } - else if (alias_map.count(bit)) - alias_map[new_bit] = alias_map.at(bit); else alias_map[new_bit] = bit; output_bits.erase(bit); |