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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /backends/autotest/autotest.cc | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
| download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'backends/autotest/autotest.cc')
| -rw-r--r-- | backends/autotest/autotest.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index 06b2c2a93..3bb0f9d66 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -91,7 +91,7 @@ static void autotest(FILE *f, RTLIL::Design *design) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - for (auto it = design->modules.begin(); it != design->modules.end(); it++) + for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) { std::map<std::string, int> signal_in; std::map<std::string, std::string> signal_const; @@ -292,7 +292,7 @@ static void autotest(FILE *f, RTLIL::Design *design) fprintf(f, "initial begin\n"); fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n"); fprintf(f, "\t// $dumpvars(0, testbench);\n"); - for (auto it = design->modules.begin(); it != design->modules.end(); it++) + for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) if (!it->second->get_bool_attribute("\\gentb_skip")) fprintf(f, "\t%s;\n", idy(it->first, "test").c_str()); fprintf(f, "\t$finish;\n"); |