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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 11:32:10 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 11:32:10 -0700 |
commit | f890cfb63b71ae7b09e19c290ec70c358dcbe9cd (patch) | |
tree | ea7602c378e794b5e7448361ba2a41d2d6a49c13 /backends/blif/blif.cc | |
parent | ab1d63a56595f11e10a5326bd83ce84d08badabe (diff) | |
parent | 78b30bbb1102047585d1a2eac89b1c7f5ca7344e (diff) | |
download | yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.tar.gz yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.tar.bz2 yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.zip |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'backends/blif/blif.cc')
-rw-r--r-- | backends/blif/blif.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index f32b0f533..b6e38c16c 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -377,7 +377,7 @@ struct BlifDumper f << stringf("\n"); RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); for (int i = 0; i < (1 << width); i++) - if (mask[i] == RTLIL::S1) { + if (mask[i] == State::S1) { for (int j = width-1; j >= 0; j--) { f << ((i>>j)&1 ? '1' : '0'); } |