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author | eddiehung <e.hung@imperial.ac.uk> | 2015-05-03 12:53:09 +0100 |
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committer | eddiehung <e.hung@imperial.ac.uk> | 2015-05-03 12:53:09 +0100 |
commit | 7c623182393aa2e8445336a99f0cfd4bc7c7e88f (patch) | |
tree | 2ff4da2da0cc9ff9517c8e48eb434818dc7a1887 /backends/blif | |
parent | 079c1205fec6d194114b3d031d78a23cb8e0e7f9 (diff) | |
download | yosys-7c623182393aa2e8445336a99f0cfd4bc7c7e88f.tar.gz yosys-7c623182393aa2e8445336a99f0cfd4bc7c7e88f.tar.bz2 yosys-7c623182393aa2e8445336a99f0cfd4bc7c7e88f.zip |
Fix for all zero mask
Diffstat (limited to 'backends/blif')
-rw-r--r-- | backends/blif/blif.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 3a4618a90..2734ca321 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -234,13 +234,24 @@ struct BlifDumper f << stringf(" %s", cstr(output)); f << stringf("\n"); RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); + bool one = false; for (int i = 0; i < (1 << width); i++) if (mask[i] == RTLIL::S1) { for (int j = width-1; j >= 0; j--) { f << ((i>>j)&1 ? '1' : '0'); } f << " 1\n"; + one = true; } + /* For some reason, sometimes we get LUTs with + * an all zero mask, which won't give any + * .names entries, so write one entry with + * all don't cares */ + if (!one) { + for (int j = width-1; j >= 0; j--) + f << '-'; + f << " 0\n"; + } continue; } |