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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 18:18:50 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 02:07:25 +0200 |
| commit | 69bf5c81c7cf65ccb8bd035eb45137e31a68ae86 (patch) | |
| tree | c27924c314fde30979aa0b91f8b179e71c15dd04 /backends/btor/btor.cc | |
| parent | 35ee774ea8eac9b745f93641a192341fe559fa6f (diff) | |
| download | yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.tar.gz yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.tar.bz2 yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.zip | |
Reject wide ports in some passes that will never support them.
Diffstat (limited to 'backends/btor/btor.cc')
| -rw-r--r-- | backends/btor/btor.cc | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index bc0504d64..999836882 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -728,10 +728,19 @@ struct BtorWorker log_error("Memory %s.%s has mixed async/sync write ports.\n", log_id(module), log_id(mem->memid)); - for (auto &port : mem->rd_ports) + for (auto &port : mem->rd_ports) { if (port.clk_enable) - log_error("Memory %s.%s has sync read ports.\n", + log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n", + log_id(module), log_id(mem->memid)); + if (port.wide_log2) + log_error("Memory %s.%s has wide read ports. Please use memory_narrow to convert them first.\n", + log_id(module), log_id(mem->memid)); + } + for (auto &port : mem->wr_ports) { + if (port.wide_log2) + log_error("Memory %s.%s has wide write ports. Please use memory_narrow to convert them first.\n", log_id(module), log_id(mem->memid)); + } int data_sid = get_bv_sid(mem->width); int bool_sid = get_bv_sid(1); |